Invention Grant
- Patent Title: Constructing via meshes for high performance routing on silicon chips
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Application No.: US16829374Application Date: 2020-03-25
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Publication No.: US10977414B2Publication Date: 2021-04-13
- Inventor: Sven Peyer , Christian Schulte
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L23/528 ; G06F30/394 ; H01L23/522 ; G06F30/3947 ; G06F30/392 ; G06F30/3953 ; G06F30/398

Abstract:
System and method for configuring via meshes for a semiconductor circuit having at least a bottom layer and a top layer each having a plurality of parallel conductive straps, and vias to interconnect straps in the bottom layer to the top layer to provide conductive routing pathways is disclosed. The method and system include inputting predefined criteria for the via mesh, and configuring feasible straps in the bottom layer of straps using a set of predefined rules and configuring feasible straps for the top layer, and optionally the intermediate layers using the set of predefined rules. The predefined criteria preferably includes one or all of: defining the bottom and top layer connection locations, defining a set of predefined tracks for each layer, defining the number of layers and straps in each layer, and combinations thereof.
Public/Granted literature
- US20200226317A1 CONSTRUCTING VIA MESHES FOR HIGH PERFORMANCE ROUTING ON SILICON CHIPS Public/Granted day:2020-07-16
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