Invention Grant
- Patent Title: Conductive vias in semiconductor packages and methods of forming same
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Application No.: US16570718Application Date: 2019-09-13
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Publication No.: US10978346B2Publication Date: 2021-04-13
- Inventor: Sung-Hui Huang , Hung-Pin Chang , Sao-Ling Chiu , Shang-Yun Hou , Wan-Yu Lee
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/00 ; H01L21/56 ; H01L25/18 ; H01L25/00 ; H01L23/498 ; H01L21/48 ; H01L23/48 ; H01L21/683 ; H01L25/065 ; H01L23/31

Abstract:
An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.
Public/Granted literature
- US20200006143A1 CONDUCTIVE VIAS IN SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME Public/Granted day:2020-01-02
Information query
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