Invention Grant
- Patent Title: Circuit system having compact decoupling structure
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Application No.: US16701792Application Date: 2019-12-03
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Publication No.: US10978413B2Publication Date: 2021-04-13
- Inventor: Masaru Haraguchi , Yoshitaka Fujiishi
- Applicant: AP Memory Technology Corp.
- Applicant Address: TW Hsinchu County
- Assignee: AP Memory Technology Corp.
- Current Assignee: AP Memory Technology Corp.
- Current Assignee Address: TW Hsinchu County
- Agency: Sinorica, LLC
- Main IPC: H05K1/18
- IPC: H05K1/18 ; H01L23/66 ; H01L49/02 ; H01L23/498 ; H01L25/16 ; H05K1/11 ; H01L23/538 ; H01L23/00 ; H01L23/64

Abstract:
A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.
Information query