Invention Grant
- Patent Title: Synchronized reset for a circuit emulator
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Application No.: US16218079Application Date: 2018-12-12
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Publication No.: US10996723B1Publication Date: 2021-05-04
- Inventor: Quang Nguyen , Duc Dang , Raju Joshi , David Abada , Akash Sharma , Zhanhe Shi
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F1/24
- IPC: G06F1/24 ; G06F1/10

Abstract:
A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.
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