Invention Grant
- Patent Title: Enabling high speed command address interface for random read
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Application No.: US16431511Application Date: 2019-06-04
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Publication No.: US10997097B2Publication Date: 2021-05-04
- Inventor: Sneha Bhatia , Vinayak Ghatawade
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G11C7/10 ; G06F13/12

Abstract:
A memory device includes a memory controller to transmit or receive input/output (“I/O”) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.
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