Invention Grant
- Patent Title: Integrated circuit with asymmetric mirrored layout analog cells
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Application No.: US16219573Application Date: 2018-12-13
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Publication No.: US10997354B2Publication Date: 2021-05-04
- Inventor: Yu-Tao Yang , Wen-Shen Chou , Yung-Chow Peng
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06F30/398
- IPC: G06F30/398 ; G03F1/36 ; G06F30/392 ; G06F30/39

Abstract:
In a first integrated circuit column, a first cell active area top edge is separated by a first separation distance from a first barrier line, a first cell active area bottom edge is separated by a second separation distance from a second barrier line, a second cell active area top edge is separated by the second separation distance from a third barrier line, and a second active area bottom edge is separated by the first separation distance from a fourth barrier line. In a second column a third cell active area top edge is separated from a fifth barrier line by the first distance, and a third cell active area bottom edge is separated from a sixth barrier line by a third distance. The first and third separation distances are different from the second separation distance. The first barrier line aligns with the fifth barrier line.
Public/Granted literature
- US20190286783A1 INTEGRATED CIRCUIT WITH ASYMMETRIC MIRRORED LAYOUT ANALOG CELLS Public/Granted day:2019-09-19
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