Memory device including noise-suppressing mechanism
Abstract:
A memory device that includes a driver IC, a voltage-dividing resistor, at least two noise-suppressing resistors and at least three memory ICs is provided. A terminal of the voltage-dividing resistor is electrically coupled to a voltage source and another other terminal of the voltage-dividing resistor is electrically coupled to the driver IC through an end a connection path. One of the memory ICs is electrically coupled to the voltage-dividing resistor and the driver IC through the end the connection path. Each of at least two of the other memory ICs is electrically coupled to the connection path through one of the noise-suppressing resistors and is further electrically coupled to the driver IC.
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