Apparatuses, systems, and methods for latch reset logic. Banks may have local latches which are coupled between a global data bus and the bank. Some of the local latches may be shared local latches which are coupled to a first bank and a second bank. The shared latches may latch data responsive to a first clock signal and a second clock signal, and may reset responsive to a combined reset signal. A reset logic circuit may receive the clock signals and a first and second reset signal. The reset logic circuit may provide the combined reset signal based on the first and second clock signals and reset signals. The clocks signals may be column active commands and the reset signals may be waveforms (e.g., falling edges) of row active commands used as part of access operations on the first or the second memory bank.