Invention Grant
- Patent Title: Process and method for achieving high immunity to ultrafast high voltage transients across inorganic galvanic isolation barriers
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Application No.: US16832356Application Date: 2020-03-27
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Publication No.: US10998278B2Publication Date: 2021-05-04
- Inventor: Jeffrey Alan West , Thomas Dyer Bonifield , Yoshihiro Takei , Mitsuhiro Sugimoto
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L23/64
- IPC: H01L23/64 ; H01L25/18

Abstract:
A microelectronic device contains a high voltage component having an upper plate and a lower plate. The upper plate is isolated from the lower plate by a main dielectric between the upper plate and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the upper plate and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer of silicon nitride having a refractive index between 2.11 and 2.23. The lower-bandgap dielectric layer extends beyond the upper plate continuously around the upper plate. The lower-bandgap dielectric layer has an isolation break surrounding the upper plate at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the upper plate.
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