A semiconductor memory device includes a control circuit, first wirings, second wirings intersecting the first wirings, and memory cells formed between the first wirings and the second wirings. The control circuit is configured to supply, in a set operation, a set pulse between one of the first wirings and one of the second wirings, supply, in a reset operation, a reset pulse between one of the first wirings and one of the second wirings, and supply, in a first operation, a first pulse between one of the first wirings and one of the second wirings. The first pulse has an amplitude larger than a larger one of an amplitude of the set pulse or an amplitude of the reset pulse, or the same amplitude as the larger amplitude. The first pulse has a pulse width larger than a pulse width of the reset pulse.