Fractional N PLL with sigma-delta noise cancellation
Abstract:
An apparatus is disclosed that includes a phase detector circuit for generating a first pulse signal based on first and second input clock signals. A first circuit adjusts the first pulse signal by delaying transmission of a leading edge of the first pulse signal, but not a trailing edge of the first pulse signal. A charge pump circuit charges or discharges a capacitor based on the adjusted first pulse signal, and a voltage controlled oscillator (VCO) circuit generates an output clock signal with a frequency that depends on a voltage on the capacitor.
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