Invention Grant
- Patent Title: Multi-column interleaved DIMM placement and routing topology
-
Application No.: US16398861Application Date: 2019-04-30
-
Publication No.: US11004476B2Publication Date: 2021-05-11
- Inventor: Hoi San Leung , Steve Zhijian Chen , Richard Jiang Li , Minh-Thanh T. Vo , Shameem Ahmed , Kenny Lieu
- Applicant: Cisco Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cisco Technology, Inc.
- Current Assignee: Cisco Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Behmke Innovation Group LLC
- Agent James M. Behmke; Jonathon P. Western
- Main IPC: G11C5/04
- IPC: G11C5/04 ; G11C5/06 ; H05K1/18 ; G06F30/392 ; G06F30/394

Abstract:
In one embodiment, a printed circuit board (PCB) has a first central processing unit (CPU) socket and a second CPU socket substantially in line with the first CPU socket, and also has a first plurality of dual in-line memory module (DIMM) sockets interconnected with the first CPU socket and a second plurality of DIMM sockets interconnected with the second CPU socket (in a direction parallel to the first plurality of DIMM sockets). The first plurality of DIMM sockets are arranged on the PCB in at least a first column and a second column of DIMM sockets, and the second plurality of DIMM sockets are arranged on the PCB in at least the second column and a third column of DIMM sockets, such that the second column of DIMM sockets contains interleaved DIMM sockets from each of the first plurality of DIMM sockets and the second plurality of DIMM sockets.
Public/Granted literature
- US20200349983A1 MULTI-COLUMN INTERLEAVED DIMM PLACEMENT AND ROUTING TOPOLOGY Public/Granted day:2020-11-05
Information query