This invention provide a PWM outputting circuit that, from pattern data represented by a plurality of bits representing a pulse width, generates a pulse width modulation signal, wherein the circuit comprises a multi-phase-clock generating circuit which generates a multi-phase clock which is a plurality of clocks of mutually different phases; an edge-pulse generating circuit which, from the pattern data that is inputted, detects a bit position of a rising-edge and a bit position of a falling-edge in the pulse width modulation signal, and generates a rising-edge-pulse and a falling-edge-pulse based on the detection; and an SR latch circuit which, by the rising-edge-pulse being inputted to a set terminal and the falling-edge-pulse being inputted to a reset terminal, generates and outputs the pulse width modulation signal.