An integrated circuit having logic and static random-access memory (SRAM) devices includes at least three active regions with gate terminals. Dielectric pillars are disposed between the active regions of the integrated circuit. A pillar is disposed symmetrically between two active regions of the logic device. A pillar is disposed asymmetrically between a p-channel field effect transistor (pFET), and an n-channel field effect transistor (nFET) of the SRAM device.