Invention Grant
- Patent Title: Multi-bit memory system with adaptive read voltage controller
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Application No.: US16397241Application Date: 2019-04-29
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Publication No.: US11017863B2Publication Date: 2021-05-25
- Inventor: Tsukasa Tokutomi , Masanobu Shirakawa , Marie Takada
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2017-060481 20170327
- Main IPC: G11C16/26
- IPC: G11C16/26 ; G11C16/34 ; G11C16/04 ; G11C11/56

Abstract:
According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
Public/Granted literature
- US10902923B2 Multi-bit memory system with adaptive read voltage controller Public/Granted day:2021-01-26
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