Invention Grant
- Patent Title: Integrated circuit with a fin and gate structure and method making the same
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Application No.: US16730192Application Date: 2019-12-30
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Publication No.: US11018246B2Publication Date: 2021-05-25
- Inventor: Kuo-Cheng Chiang , Teng-Chun Tsai , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/161 ; H01L21/8234 ; H01L27/088 ; H01L21/8238 ; H01L27/092 ; H01L21/762 ; H01L29/78 ; H01L29/165
Abstract:
The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
Information query
IPC分类:
