Invention Grant
- Patent Title: Three dimensional vertically structured electronic devices
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Application No.: US14990612Application Date: 2016-01-07
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Publication No.: US11018253B2Publication Date: 2021-05-25
- Inventor: Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
- Applicant: Lawrence Livermore National Security, LLC
- Applicant Address: US CA Livermore
- Assignee: Lawrence Livermore National Security, LLC
- Current Assignee: Lawrence Livermore National Security, LLC
- Current Assignee Address: US CA Livermore
- Agency: Zilka-Kotab, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/778 ; H01L29/20 ; H01L29/205 ; H01L29/808 ; H01L29/66 ; H01L29/06
Abstract:
According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.
Public/Granted literature
- US20170200820A1 THREE DIMENSIONAL VERTICALLY STRUCTURED ELECTRONIC DEVICES Public/Granted day:2017-07-13
Information query
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