Invention Grant
- Patent Title: Embedded test circuitry and method therefor
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Application No.: US16522714Application Date: 2019-07-26
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Publication No.: US11018635B2Publication Date: 2021-05-25
- Inventor: Stephane Thuriés , Birama Goumballa , Cristian Pavao Moreira
- Applicant: NXP USA, INC.
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Priority: EP18306116 20180814
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H03F1/52 ; H03F3/213 ; H03F3/45

Abstract:
A circuit (200) for testing failure of a connection between a radio frequency, RF, integrated circuit (201) and external circuitry (204), the circuit comprising: an amplifier (205) having first and second input paths (215, 216) and first and second output paths (206, 207); a first power detector (208, 209) coupled to one of said first or second output paths; at least one connection (211) between said first and second output paths (206, 207) and said external circuitry (204), connecting said outputs to a RF combiner (210) said external circuitry; at least one disabling circuit (230, 232, 234, 236, 240, 242, 260, 262) coupled to at least one of said first and second output paths (206, 207) or at least one of said first and second input path (215, 216), before said path reaches said power detector (208, 209); for disabling one of said inputs or outputs; wherein when said input or output path is disabled (206, 207), and a signal is output along the enabled output path (206, 207), the power detector (208, 209) on said disabled output path can detect if there is a failure in said at least one connection (211).
Public/Granted literature
- US20200059203A1 EMBEDDED TEST CIRCUITRY AND METHOD THEREFOR Public/Granted day:2020-02-20
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