Invention Grant
- Patent Title: Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit
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Application No.: US16353409Application Date: 2019-03-14
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Publication No.: US11023559B2Publication Date: 2021-06-01
- Inventor: John L. McCollum , Jonathan W. Greene , Gregory William Bakker
- Applicant: Microsemi SoC Corp.
- Applicant Address: US CA San Jose
- Assignee: Microsemi SoC Corp.
- Current Assignee: Microsemi SoC Corp.
- Current Assignee Address: US CA San Jose
- Agency: Glass and Associates
- Agent Kenneth D'Alessandro; Kenneth Glass
- Main IPC: G06F17/16
- IPC: G06F17/16 ; G06G7/161 ; G06G7/22 ; G06N3/04 ; G06N3/063

Abstract:
A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.
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Information query