Invention Grant
- Patent Title: Pseudo-asynchronous digital circuit design
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Application No.: US16313901Application Date: 2017-06-29
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Publication No.: US11023632B2Publication Date: 2021-06-01
- Inventor: Itamar Levi , Osnat Keren , Alexander Fish
- Applicant: Bar-Ilan University
- Applicant Address: IL Ramat-Gan
- Assignee: Bar-Ilan University
- Current Assignee: Bar-Ilan University
- Current Assignee Address: IL Ramat-Gan
- International Application: PCT/IL2017/050732 WO 20170629
- International Announcement: WO2018/002939 WO 20180104
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F30/327 ; G06F21/55 ; H04L9/00 ; H04L9/12 ; H03K19/00 ; G06F21/75 ; H03K19/003 ; G06F119/06

Abstract:
A logic element includes a logic block, a supply voltage input, switchable power gates and a gate selector. The logic block implements a logic function on input data to obtain at least one output data signal. The switchable power gates transfer a supply voltage from the supply voltage input to the logic block in accordance with respective gate control signals. At least two of the power gates have different respective electrical properties. The gate selector switches on differing ones of the power gates in accordance with gate selection data.
Public/Granted literature
- US20200082031A1 PSEUDO-ASYNCHRONOUS DIGITAL CIRCUIT DESIGN Public/Granted day:2020-03-12
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