Invention Grant
- Patent Title: High-level synthesis method, high-level synthesis apparatus, and high-level synthesis system
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Application No.: US16820204Application Date: 2020-03-16
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Publication No.: US11023633B2Publication Date: 2021-06-01
- Inventor: Shintaro Imamura
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JPJP2019-057749 20190326
- Main IPC: G06F30/327
- IPC: G06F30/327 ; G06F115/02

Abstract:
Disclosed herein is a method of generating an RTL description that implements any functional safety system. A high-level synthesis method for generating an RTL description in which a functional safety system is inserted by using an operation description defining a functional logic, a high-level synthesis script defining a high-level synthesis constraint, and a functional safety system implementation specification specifying a functional safety system to be inserted in a high-level synthesis process. The high-level synthesis method includes a control data flow graph generation step in which a high-level synthesis unit generates a control data flow graph using the operation description, and a first function safety system insertion processing step in which the high-level synthesis unit inserts the function safety system into the control data flow graph according to the function safety system implementation specification after the control data flow graph generation step.
Public/Granted literature
- US20200311328A1 HIGH-LEVEL SYNTHESIS METHOD, HIGH-LEVEL SYNTHESIS APPARATUS, AND HIGH-LEVEL SYNTHESIS SYSTEM Public/Granted day:2020-10-01
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