Invention Grant
- Patent Title: Hierarchical clock tree construction based on constraints
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Application No.: US16664791Application Date: 2019-10-25
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Publication No.: US11023646B2Publication Date: 2021-06-01
- Inventor: Sridhar Subramaniam , Hongda Lu , Kok-Hoong Chiu
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Renaissance IP Law Group LLP
- Main IPC: G06F1/10
- IPC: G06F1/10 ; G06F30/396 ; G06F1/08 ; G06F30/30 ; G06F30/392 ; G06F30/394 ; G06F30/398 ; G06F30/3312 ; G06F119/12

Abstract:
A method of automatically constructing a hierarchical clock tree for an integrated circuit may include constructing a global clock tree on a first level based on first-level constraints, pushing the global clock tree to partitions on a second level, and generating second-level constraints for the partitions on the second level. The second-level constraints may be included in configuration files that may be generated for the partitions on the second level. The first-level constraints may be included in a first-level configuration file that is user-modifiable. The second-level constraints may include information for replicating multiple instantiated partitions on the second level. The method may further include modifying terminal names and/or configurations after pushdown. The method may further include creating infrastructure to analyze timing of the global clock tree.
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