A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.