Invention Grant
- Patent Title: Process for molding a back side wafer singulation guide
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Application No.: US16449885Application Date: 2019-06-24
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Publication No.: US11024541B2Publication Date: 2021-06-01
- Inventor: Neftali Salazar , Rommel Quintero , Thomas Scott Morris
- Applicant: Qorvo US, Inc.
- Applicant Address: US NC Greensboro
- Assignee: Qorvo US, Inc.
- Current Assignee: Qorvo US, Inc.
- Current Assignee Address: US NC Greensboro
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/683 ; H01L21/56 ; H01L23/00 ; H01L23/498

Abstract:
A process for molding a back side wafer singulation guide is disclosed. Structures for heat mitigation include an overmold formed over a contact surface of a device layer of a wafer, covering bump structures. The overmold and bump structures are thinned and planarized, and the overmold provides an underfill to increase interconnect reliability of a semiconductor die in a flip chip bonded package. However, visibility of singulation guides on the contact surface is obstructed. A channel is formed extending through the device layer and into the handle layer, and is filled with the overmold. The handle layer is replaced with a thermally-conductive molding layer formed on the back side for dissipating heat generated by semiconductor devices. The thermally-conductive handle is thinned until the overmold in the channel beneath the device layer is exposed. The exposed overmold provides a visible back side singulation guide for singulating the wafer.
Information query
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