Invention Grant
- Patent Title: Complementary MOS FETS vertically arranged and including multiple dielectric layers surrounding the MOS FETS
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Application No.: US16201328Application Date: 2018-11-27
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Publication No.: US11024548B2Publication Date: 2021-06-01
- Inventor: Mark Van Dal , Gerben Doornbos
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/423 ; H01L29/06 ; H01L29/786 ; H01L29/66 ; H01L21/02 ; H01L27/092 ; H01L29/78 ; H01L21/822 ; H01L27/06 ; H01L27/11
Abstract:
A fin including a bottom portion, a first sacrificial layer disposed over the bottom portion, a first semiconductor layer disposed over the first sacrificial layer, a second sacrificial layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the second sacrificial layer, is formed. The second semiconductor layer protrudes from a first insulating layer. A dummy gate is formed over the second semiconductor layer. A sidewall spacer layer is formed on side faces of the dummy gate. A first dielectric layer is formed over the dummy gate and the sidewall spacer layer. The dummy gate is removed, thereby forming a gate space. The first insulating layer is etched in the gate space, thereby exposing the first semiconductor layer and the first and second sacrificial layers. The first and second sacrificial layers are removed. A gate dielectric layer and a gate electrode layer are formed.
Public/Granted literature
- US20190148243A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE Public/Granted day:2019-05-16
Information query
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