Invention Grant
- Patent Title: Nanowire transistor fabrication with hardmask layers
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Application No.: US16149056Application Date: 2018-10-01
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Publication No.: US11024714B2Publication Date: 2021-06-01
- Inventor: Seung Hoon Sung , Seiyon Kim , Kelin J. Kuhn , Willy Rachmady , Jack T. Kavalieros
- Applicant: Sony Corporation
- Applicant Address: JP Tokyo
- Assignee: Sony Corporation
- Current Assignee: Sony Corporation
- Current Assignee Address: JP Tokyo
- Agency: Michael Best & Friedrich LLP
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/66 ; H01L29/06 ; H01L29/786 ; H01L29/423 ; H01L29/775 ; B41F3/46 ; B41F17/08 ; B41N10/04 ; H01L21/033 ; H01L29/78

Abstract:
A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.
Public/Granted literature
- US20190043948A1 NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS Public/Granted day:2019-02-07
Information query
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