An information processing system includes a first processor, a second processor, a first buffer circuit, a second buffer circuit, and a first memory, wherein the first processor is configured to generate a first read command specifying a first data stored in a first address area of the first memory, the second processor is configured to, based on the first read command, generate a second read command specifying a second data stored in a second address area of the first memory, the first buffer circuit is configured to store the first read command, the second buffer circuit is configured to store the second read command, the second processor is configured to execute the first read command stored in the first buffer circuit, and the second processor is configured to execute the second read command stored in the second buffer circuit when the first buffer circuit is in an empty state.