Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) comprises a first cell including one or more first type gate-all-around (GAA) transistors located in a first region of the integrated circuit; a second cell including one or more second type GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type GAA transistors are one of nanosheet transistors or nanowire transistors and the second type GAA transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.