Methods, systems, and devices for low power mode for a memory device are described. A memory device may identify a pattern of data configured to be stored in an array of memory cells and determine if the pattern of data satisfies a criterion. The pattern of data may satisfy the criterion if each of the bits of data include a same logic value. If the pattern of data satisfies the criterion, the memory device may disable a driver of an internal bus of the memory device if the data satisfies the criterion, isolate a data line from the internal bus, or couple the data line with a voltage source, or a combination thereof. The memory device may further disable a signal of a clock tree based on identifying that the pattern of data satisfies the criterion.