Invention Grant
- Patent Title: Technique for processing a sequence of atomic add with carry instructions when a data value is not present in a cache
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Application No.: US16661196Application Date: 2019-10-23
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Publication No.: US11036500B2Publication Date: 2021-06-15
- Inventor: Andreas Due Engh-Halstvedt
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Priority: GB1422785.4 20141219
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F12/0875 ; G06F7/50

Abstract:
Processing circuitry performs processing operations specified by program instructions. An instruction decoder decodes an atomic-add-with-carry instruction AADDC to control the processing circuitry to perform an atomic operation of an add of an addend operand value and a data value stored in a memory to generate a result value stored in the memory and a carry value indicative of whether or not the add generated a carry out. The atomic-add-with-carry instructions may be used within systems which accumulate a local sum value prior to a data value being returned into a local cache memory at which time the local sum value is added to the return data value. The atomic-add-with-carry instructions may also be used in embodiments comprising a coalescing tree of respective processing apparatus where the carry out values generated from local sums produced at each node are returned early to higher nodes within the hierarchy thereby releasing them to commence other processing.
Public/Granted literature
- US20200057636A1 ATOMIC ADD WITH CARRY INSTRUCTION Public/Granted day:2020-02-20
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