Invention Grant
- Patent Title: Semiconductor device and dynamic logic circuit
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Application No.: US16759013Application Date: 2018-11-12
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Publication No.: US11037622B2Publication Date: 2021-06-15
- Inventor: Tomoaki Atsumi , Kiyoshi Kato , Shuhei Maeda
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi
- Agency: Robinson Intellectual Property Law Office
- Agent Eric J. Robinson
- Priority: JPJP2017-225312 20171124,JPJP2018-169677 20180911
- International Application: PCT/IB2018/058852 WO 20181112
- International Announcement: WO2019/102293 WO 20190531
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/4094 ; H01L27/108 ; H01L29/786

Abstract:
A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.
Public/Granted literature
- US20200265887A1 SEMICONDUCTOR DEVICE AND DYNAMIC LOGIC CIRCUIT Public/Granted day:2020-08-20
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