Invention Grant
- Patent Title: Column erasing in non-volatile memory strings
-
Application No.: US16252300Application Date: 2019-01-18
-
Publication No.: US11037631B2Publication Date: 2021-06-15
- Inventor: Jayavel Pachamuthu , Amul Dhirajbhai Desai , Ankitkumar Babariya
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Agency: Volpe Koenig
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/16 ; G11C16/34

Abstract:
Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit.
Public/Granted literature
- US20200013469A1 COLUMN ERASING IN NON-VOLATILE MEMORY STRINGS Public/Granted day:2020-01-09
Information query