Invention Grant
- Patent Title: Method of manufacturing semiconductor device
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Application No.: US16601234Application Date: 2019-10-14
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Publication No.: US11037830B2Publication Date: 2021-06-15
- Inventor: Naoki Takizawa , Tatsuyoshi Mihara
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/28 ; H01L29/66 ; H01L27/1157 ; H01L27/11573 ; H01L21/306 ; H01L29/423

Abstract:
After the step of polishing, a part of each of each gate electrode is removed such that the upper surface of each gate electrode is located closer than the damaged region formed in the gate insulating film located between the gate electrodes to the main surface of the semiconductor substrate in cross-section view. Thus, it is possible to suppress the occurrence of a short-circuit defect during the operation of the semiconductor device.
Public/Granted literature
- US20210111256A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2021-04-15
Information query
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