Invention Grant
- Patent Title: Interconnect structure for package-on-package devices
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Application No.: US16683672Application Date: 2019-11-14
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Publication No.: US11037861B2Publication Date: 2021-06-15
- Inventor: Jui-Pin Hung , Jing-Cheng Lin , Po-Hao Tsai , Yi-Jou Lin , Shuo-Mao Chen , Chiung-Han Yeh , Der-Chyang Yeh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/12
- IPC: H01L23/12 ; H01L21/00 ; H01L23/48 ; H01L23/00 ; H01L23/528 ; H01L25/065 ; H01L23/538 ; H01L23/28 ; H01L23/498 ; H01L21/56 ; H01L25/10 ; H01L21/768 ; H01L21/82 ; H01L25/18 ; H01L25/00 ; H01L21/48 ; H01L23/31
Abstract:
An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
Public/Granted literature
- US20200083145A1 Interconnect Structure for Package-on-Package Devices Public/Granted day:2020-03-12
Information query
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