Invention Grant
- Patent Title: Plane-less voltage reference interconnects
-
Application No.: US16450287Application Date: 2019-06-24
-
Publication No.: US11037874B2Publication Date: 2021-06-15
- Inventor: Bok Eng Cheah , Jackson Chung Peng Kong , Jenny Shio Yin Ong , Seok Ling Lim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Priority: MYPI2018704000 20181029
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/522 ; H01L23/552 ; H01L23/528 ; H01L23/00

Abstract:
An electronic device comprises an integrated circuit (IC) die including a first plurality of contact pads; and a plurality of stacked interconnect layers. The plurality of stacked interconnect layer include a first interconnect layer including a first conductive plane, a first vertical interconnect portion, and dielectric material isolating the first vertical interconnect portion from the first conductive plane; and a second interconnect layer including a second conductive plane contacting the first conductive plane, a second vertical interconnect portion contacting the first vertical interconnect portion, and the dielectric material isolating the second vertical interconnect portion from the second conductive plane; wherein the first and second vertical interconnect portions are included in a first vertical interconnect through the first and second conductive planes that contacts a first contact pad of the first plurality of contact pads.
Information query
IPC分类: