Insulated gate bipolar transistor device having a fin structure
Abstract:
A transistor device includes a first silicon nanowire array-MOSFET and a second silicon nanowire array-MOSFET integrated with a bulk drift region. The first silicon nanowire array-MOSFET is configured as an n-MOSFET by substantially only accommodating an electron current, and the second silicon nanowire array-MOSFET is configured as a p-MOSFET by substantially only accommodating a hole electron current. A current strength of a current through the first silicon nanowire array-MOSFET caused by electrons is at least 10 times larger than a current through the first silicon nanowire array-MOSFET caused by holes in an on-state of the transistor device. Further embodiments of transistor devices are described.
Public/Granted literature
Information query
Patent Agency Ranking
0/0