Invention Grant
- Patent Title: Transistors and methods of forming transistors
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Application No.: US16539172Application Date: 2019-08-13
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Publication No.: US11038038B2Publication Date: 2021-06-15
- Inventor: Yoichi Fukushima , Takuya Imamoto
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L29/66 ; H01L29/78 ; H01L29/40 ; H01L27/108

Abstract:
Some embodiments include a transistor having a gate, with the gate being over a semiconductor base. The gate has sidewalls. A channel region is under the gate. Spacers are along the sidewalk. The spacers each include a spacer structure and a void between the spacer structure and the gate. The spacer structures each include a vertical segment extending upwardly from a horizontal segment. The vertical segments join to the horizontal segments at corners. Source/drain regions are adjacent the channel region. The voids may be along the entirety of the vertical segments of the spacer structures, and may extend around the corners and to under the horizontal segments of the spacer structures. Additionally, or alternatively, bottoms of the voids may be adjacent fill material which includes silicon, nitrogen, boron and oxygen. Some embodiments include methods of forming transistors.
Public/Granted literature
- US20210050428A1 Transistors and Methods of Forming Transistors Public/Granted day:2021-02-18
Information query
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