- Patent Title: Step height mitigation in resistive random access memory structures
-
Application No.: US16422207Application Date: 2019-05-24
-
Publication No.: US11038108B2Publication Date: 2021-06-15
- Inventor: Wei-Ming Wang , Chia-Wei Liu , Jen-Sheng Yang , Wen-Ting Chu , Yu-Wen Liao , Huei-Tzu Wang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.
Public/Granted literature
- US20200373487A1 STEP HEIGHT MITIGATION IN RESISTIVE RANDOM ACCESS MEMORY STRUCTURES Public/Granted day:2020-11-26
Information query
IPC分类: