Invention Grant
- Patent Title: Power distribution for active-on-active die stack with reduced resistance
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Application No.: US15902703Application Date: 2018-02-22
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Publication No.: US11041211B2Publication Date: 2021-06-22
- Inventor: Praful Jain
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; C12Q1/6886 ; G01N33/574 ; C07K16/32

Abstract:
Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack structure near a bottom surface of the first substrate is interconnected to a lower end of the TSV. A power distribution network layer of the second stack structure is located between lower and upper layers of the metal layers thereof. A transistor located at least in part in the second substrate is interconnected to the power distribution network layer to receive supply voltage or ground.
Public/Granted literature
- US20190259702A1 POWER DISTRIBUTION FOR ACTIVE-ON-ACTIVE DIE STACK WITH REDUCED RESISTANCE Public/Granted day:2019-08-22
Information query
IPC分类: