Invention Grant
- Patent Title: Zero-pin test solution for integrated circuits
-
Application No.: US16589968Application Date: 2019-10-01
-
Publication No.: US11041904B2Publication Date: 2021-06-22
- Inventor: Tapan Jyoti Chakraborty , Umesh Srikantiah , Rachana Rout
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson+Sheridan, L.L.P.
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3177

Abstract:
In some aspects, the present disclosure provides a method for testing an integrated circuit (IC). In some configurations, the method includes determining, by a test controller embedded in the IC, a change in operation of the IC from a normal mode to a test mode. The method also includes communicating, by the test controller to a chain of data storage elements in the IC: a first test signal configured to change an input/output (I/O) function of a first IC pin, and a second test signal configured to apply one of a plurality of test functions to each data storage element in the chain of data storage elements. The method also includes, receiving, via a second IC pin, a test clock signal configured to control a latch function of each data storage element in the chain of data storage elements.
Public/Granted literature
- US20210096182A1 ZERO-PIN TEST SOLUTION FOR INTEGRATED CIRCUITS Public/Granted day:2021-04-01
Information query