A multiple scalable radar on chip (SROC) based system in a multi-array configuration; may include: a first SROC; and a second SROC. The first SROC may include a ramp generator, a fractional-N PLL synthesizer, a frequency multiplier, a power amplifier, ‘Y’ number of transmitter chains, ‘Z’ number of receiver chains, and a receiver section. The second SROC may include a ramp generator, a fractional-N PLL synthesizer, a frequency multiplier, a power amplifier, ‘Y’ number of transmitter chains, ‘Z’ number of receiver chains, and a receiver section. The ramp generator of the first SROC may be configured to drive the fractional-N PLL synthesizer of the second SROC. The fractional-N PLL synthesizer of the second SROC may be configured to produce radio frequency (RF) ramp signals to drive both the first and second SROCs. ‘Y’ and ‘Z’ may represent positive integers.