A circuit comprises a burst clock control and gating device configured to generate a modified clock signal in a test mode by allowing a preset number of clock pulses of a clock signal to go through during each clock cycle of a reference clock signal, and a plurality of clock gating devices. Each of the plurality of clock gating devices comprises a multiplexing device, wherein the modified clock signal is coupled to a selector input of the multiplexing device, and input signal generation circuitry configured to ensure the timing of the transitions on the output are derived purely from the timing of the transitions of the clock and not by the timing of the transition of the first and second inputs of the multiplexer.