Invention Grant
- Patent Title: Determining a transfer rate for channels of a memory system
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Application No.: US16535771Application Date: 2019-08-08
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Publication No.: US11042304B2Publication Date: 2021-06-22
- Inventor: Mitsuru Anazawa
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Priority: JPJP2019-048742 20190315
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F3/06 ; G06F13/00 ; G06F13/28

Abstract:
A memory system includes first and second non-volatile memories and a memory controller respectively connected to the first and second non-volatile memories via first and second channels. The memory controller executes a first read operation of reading first data from the first non-volatile memory and a second read operation of reading second data from the second non-volatile memory in parallel in response to a first read request received from the outside, and sets a first transfer rate of the first channel to be lower than a second transfer rate of the second channel when a first time at which the first read operation is scheduled to be completed is earlier than a second time at which the second read operation is scheduled to be completed.
Public/Granted literature
- US20200293198A1 MEMORY SYSTEM Public/Granted day:2020-09-17
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