Invention Grant
- Patent Title: Semiconductor device including an adder
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Application No.: US16565679Application Date: 2019-09-10
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Publication No.: US11042359B2Publication Date: 2021-06-22
- Inventor: Nobuaki Sakamoto
- Applicant: Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
- Applicant Address: JP Minato-ku; JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee Address: JP Minato-ku; JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JPJP2019-042161 20190308
- Main IPC: G06F7/53
- IPC: G06F7/53 ; G06F7/533

Abstract:
According to the embodiments, a semiconductor device includes: an adder configured to generate positive multiple data of the multiplicand which is used for a plurality of the multiplication in plurality and does not include a value of 2n (n is a positive integer) of the multiplicand; a Wallace tree circuit provided in each of the multiplier circuits and configured to operate a sum of a plurality of partial products by using a plurality of adders; and a selection circuit provided in each of the multiplier circuits and configured to select, according to a plurality of bits selected from the multiplier, data falling in a multiple of one of the multiplicand, data of 2n of the multiplicand, and the positive multiple data from the adder in order to output as one partial product of the plurality of partial products to the Wallace tree circuit.
Public/Granted literature
- US20200285445A1 SEMICONDUCTOR DEVICE Public/Granted day:2020-09-10
Information query
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