Systems and methods for selective communication through a DIMM socket via a multiplexer. A system comprises a computer interface board that includes at least two DIMM sockets, a communication bus circuitry and a control circuitry coupled to the at least two DIMM sockets. The communication bus circuitry includes a first portion of a first bus configured to receive a first set of data, and a second portion of the first bus configured to receive a second set of the data. The control circuitry includes a multiplexer coupled to a first DIMM socket and the first portion of the first bus, the first multiplexer configured to enable the control circuitry to selectively communicate through the first DIMM socket, via the first portion of the first bus, using one of the number of communication protocols.