Methods for generating a cell set for an analog design tool are disclosed. A method comprises receiving, at a cell generator, one or more electronic files of a process-specific architectural cell (AP_Cell) having wiring for power and ground, FILL, wherein the AP_Cell is configured according to a first manufacturing process. The method further includes receiving, at the cell generator, one or more electronic files of a schematic cell (S_Cell) having internal wiring between circuit elements to provide a function for the S_Cell. The method also includes merging data from the one or more electronic files of the AP_Cell and the one or more electronic files of the S_Cell to generate a process-specific schematic cell (SP_Cell) used as a building block for a physical layout of an analog IC, wherein the process-specific schematic cell comprises one or more electronic files. Related devices are also described herein.