Invention Grant
- Patent Title: Low offset and enhanced write margin for stacked fabric dies
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Application No.: US16683846Application Date: 2019-11-14
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Publication No.: US11043263B1Publication Date: 2021-06-22
- Inventor: Sree R K C Saraswatula , Abhimanyu Kumar , Santosh Yachareni , Shidong Zhou
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C11/419 ; G11C7/10 ; G11C11/412
Abstract:
A device includes an amplifier, a plurality of selector circuitries, and a plurality of fabric dies. The amplifier is configured to output a supply power signal. Each selector circuitry of the plurality of selector circuitries receives the supply power signal from the amplifier. Each fabric die of the plurality of fabric dies has a corresponding selector circuitry of the plurality of selector circuitries. Each selector circuitry corresponding to a die of the plurality of dies is configured to provide the supply power signal received from the amplifier to its corresponding die responsive to a selection signal being asserted. Selector circuitries of the plurality of selector circuitries corresponding to unselected dies of the plurality of dies pull address supply power for the unselected dies to an input other than the supply power signal of the selector circuitries corresponding to the unselected die.
Information query
