Invention Grant
- Patent Title: Anti-fuse structure and method for fabricating same, as well as semiconductor device
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Application No.: US16882195Application Date: 2020-05-22
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Publication No.: US11043450B2Publication Date: 2021-06-22
- Inventor: Chih Cheng Liu
- Applicant: Changxin Memory Technologies, Inc.
- Applicant Address: CN Anhui
- Assignee: Changxin Memory Technologies, Inc.
- Current Assignee: Changxin Memory Technologies, Inc.
- Current Assignee Address: CN Anhui
- Agency: Sheppard Mullin Richter & Hampton LLP
- Priority: CN201711488681.0 20171229
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L23/525 ; H01L21/311 ; H01L23/528
Abstract:
An anti-fuse structure, a method for fabricating the anti-fuse structure, and a semiconductor device are disclosed. The anti-fuse structure includes a semiconductor substrate, a fuse oxide layer, a gate material layer, a first electrode and a second electrode. An active area is defined on the semiconductor substrate by an isolation structure. The active area includes a wide portion and a narrow portion connected to each other. The fuse oxide layer is located on the semiconductor substrate, covers the narrow portion and extends to cover a first part of the wide portion. The gate material layer is formed on the fuse oxide layer. The first electrode is formed on and electrically connected to the gate material layer, while the second electrode is formed on and electrically connected to a second part of the wide portion not covered by the fuse oxide layer.
Information query
IPC分类:
