Invention Grant
- Patent Title: Low resistivity interconnects with doped barrier layer for integrated circuits
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Application No.: US16410787Application Date: 2019-05-13
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Publication No.: US11043454B2Publication Date: 2021-06-22
- Inventor: Ganesh Hegde , Harsono S. Simka
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Lewis Roca Rothgerber Christie LLP
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/768

Abstract:
A method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount.
Public/Granted literature
- US20200235055A1 LOW RESISTIVITY INTERCONNECTS FOR INTEGRATED CIRCUIT AND METHODS OF MANUFACTURING THE SAME Public/Granted day:2020-07-23
Information query
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