Invention Grant
- Patent Title: Solderless interconnection structure and method of forming same
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Application No.: US16436626Application Date: 2019-06-10
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Publication No.: US11043462B2Publication Date: 2021-06-22
- Inventor: Yu-Wei Lin , Sheng-Yu Wu , Yu-Jen Tseng , Tin-Hao Kuo , Chen-Shien Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L21/48 ; H01L23/00 ; H01L21/768 ; H01L25/065 ; H01L25/00 ; H01L23/498

Abstract:
An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
Public/Granted literature
- US20190295971A1 Solderless Interconnection Structure and Method of Forming Same Public/Granted day:2019-09-26
Information query
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